`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/17 10:19:46
// Design Name:
// Module Name: tb_vase
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module tb_vase();

reg clk_119m;
reg rst_n;

wire w_video_hs  ;
wire w_video_vs  ;
wire w_video_de  ;
wire [23:0] w_video_data;

initial begin
    clk_119m = 1'd1;
    rst_n <= 1'd0;
    #20001
    rst_n <= 1'd1;
end

always #10 clk_119m <= ~clk_119m;

vesa_data vesa_data_inst(
    .clk_119m    (clk_119m),
    .rst_n       (rst_n),

    .o_video_hs  (w_video_hs),
    .o_video_de  (w_video_de),
    .o_video_vs  (w_video_vs),
    .o_video_data(w_video_data)
);

endmodule
